1. Field of the Invention
The present invention relates to retention voltage generation in an integrated circuit. More particularly, this invention relates to the provision of a retention voltage which is stable against variations in characteristic threshold voltages of threshold devices in the integrated circuit.
2. Description of the Prior Art
The provision of a retention voltage in an integrated circuit can be used to hold components of that integrated circuit in a data retention state. For example, in a memory device, it may be desired to power down as much as possible of the memory device (for example switching off associated access circuitry) whilst reducing the voltage applied to the bitcells of the memory to a level at which information stored therein can be maintained, but keeping that voltage as low as possible to avoid power consumption through current leakage. Given that the power consumption of such advice can be logarithmic with the voltage applied, there is great motivation to provide as low a retention voltage as possible. Nevertheless, this retention voltage must be stable, such that fluctuations do not cause data loss.
Nevertheless, in the manufacture of such integrated circuits, whilst the manufacturers of such integrated circuits strive to produce the components devices of the integrated circuit within tight tolerances, some “process variations” are inevitable. In the context of the provision of a retention voltage within an integrated circuit, these process variations can lead to fluctuations in the characteristic threshold voltage of the components of the integrated circuit, which may result in variations in the retention voltage, thus risking data loss.
A relatively stable retention voltage may be provided within an integrated circuit by means of a band gap voltage regulator. However, such devices have high power consumption, and are both relatively large and complex. It would be preferable to provide a small and dense component for the provision of the retention voltage which is simply implemented and does not consume too much area.
A simple technique which is known for the provision of a retention voltage is to provide a small PMOS diode between a supply voltage node and a retention voltage node of the integrated circuit. However, it has been found that such devices can suffer from problems in corner cases of process variations, in particular when the integrated circuit comprises both PMOS and NMOS components. Most notably, particular cross corners of process variations for these components (e.g. slow-fast or fast-slow) can result in undesirably large leakage current within the components supplied with the retention voltage, leading to an increased voltage drop across the PMOS diode and hence a reduction in the supplied retention voltage. If this reduction is allowed to become too great, the data retention of the functional circuitry may fail.
Consequently, it would be desirable to provide an improved technique for providing a retention voltage in an integrated circuit which addresses the above described problems.